The present invention relates to an all-pixel readout-type solid-state image sensing device and a method of driving the same and, more particularly, to the structure of a vertical transfer electrode for transferring read signal charges to a vertical CCD (Charge Coupled Device) and setting of a driving voltage to be applied to the vertical transfer electrode.
In recent years, video cameras for business or private use, which use solid-state image sensing devices, are becoming popular. These conventional video cameras for business or private use employ the interlaced scheme (interfaced scanning scheme) with which horizontal signal lines are scanned every other line to cope with the TV scheme (NTSC or PAL).
Meantime, image input cameras for personal computers have been extensively developed recently. Cameras of this type employ, as the horizontal scanning scheme, the non-interlaced scheme to obtain high-resolution still images and easily output images to computer displays. The solid-state image sensing device used in a camera of the non-interlaced scheme must simultaneously and independently read signal charges of all pixels. This read scheme is called all-pixel readout or progressive scan (reference: Okuya et al., xe2x80x9cA ⅓-inch 330 k Square-Pixel Progressive-Scan IT-CCD Image Sensorxe2x80x9d, 1995 ITE Annual Convention, pp. 93-94, 1995).
FIG. 10 shows a conventional all-pixel readout-type interline CCD solid-state image sensing device.
This image sensing device is mainly divided into an image sensing portion 1, a horizontal CCD 2, and an output portion (charge detection portion) 3. In the image sensing portion 1, a plurality of photodiodes 4 for storing photoelectrically converted signal charges are two-dimensionally arrayed in a matrix. Vertical CCDs 5 for transferring signal charges in the vertical direction are arranged between the photodiode lines. A transfer gate region 10 for reading signal charges from each photodiode 4 to a corresponding vertical CCD 5 is formed between the photodiode 4 and the vertical CCD 5. In the image sensing portion 1, a region other than the photodiodes 4, vertical CCDs 5, and transfer gate regions 10 is an element isolation region 11.
The operation of the solid-state image sensing device with the above arrangement will be described. Signal charges photoelectrically converted by the photodiodes 4 within a predetermined period are read to the vertical CCDs 5 through the transfer gate regions 10. The signal charges read to the vertical CCDs 5 are transferred to the horizontal CCD 2 in units of horizontal lines. The signal charges transferred to the horizontal CCD 2 are transferred to the output portion 3 and detected.
FIG. 11 shows the photodiodes 4 and vertical CCDs 5 of the solid-state image sensing device shown in FIG. 10. FIG. 11 shows only 3xc3x972 pixels in the horizontal and vertical directions. FIG. 12 shows enlarged details of the structure shown in FIG. 11. FIG. 13 shows a section taken along a line Cxe2x80x94C in FIG. 12.
Referring to FIGS. 11 to 13, the vertical CCDs 5 consisting of polysilicon and having vertical transfer electrodes 6, 7, 8, and 9 are arranged between the photodiode lines. The four vertical transfer electrodes 6 to 9 are commonly formed across the vertical CCDs 5 in units of photodiodes 4. The vertical transfer electrodes 8 also serve as transfer electrodes for reading signal charges from the photodiodes 4 to the vertical CCDs 5. Referring to FIG. 13, insulating films (not shown) are formed between a semiconductor substrate 12 and the vertical transfer electrodes 6 to 9 and among the vertical transfer electrodes. Four-phase driving pulses xcfx86V1, xcfx86V2, xcfx86V3, and xcfx86V4 are applied to the vertical transfer electrodes 6, 7, 8, and 9, respectively.
A method of driving the vertical CCDs 5 of the above-described solid-state image sensing device of all-pixel readout type will be described next.
FIGS. 14A to 14D show the waveforms of driving pulses applied to the vertical transfer electrodes 6 to 9 at the time of read and during the vertical transfer period immediately after the read. FIGS. 15A to 15G show potentials representing signal charge storage and transfer states at times t0 to t5 in FIGS. 14A to 14D. The higher the driving pulse voltage becomes, the higher the potential becomes. In FIGS. 15A to 15G, the potential becomes high toward the lower side of the drawings. In other words, the potential with respect to electrons rises toward the upper side of the drawings.
At time t0, the driving pulse xcfx86V3 of high level VH is applied to the vertical transfer electrode 8 also serving as a transfer electrode (FIG. 14C) to read signal charges 30 from the photodiode 4 to the vertical CCD 5, as shown in FIG. 15B. At this time, the driving pulses xcfx86V1 and xcfx86V4 are at low level VL (FIGS. 14A and 14D), and the driving pulse xcfx86V2 is at intermediate level VM (VL less than VM less than VH) (FIG. 14B).
At time t1, the driving pulse xcfx86V3 applied to the vertical transfer electrode 8 is set at intermediate level VM (FIG. 14C), so signal charges are stored only at the lower portions of the vertical transfer electrodes 7 and 8 corresponding to the driving pulses xcfx86V2 and xcfx86V3, respectively, as shown in FIG. 15C.
At time t2, the driving pulse xcfx86V4 applied to the vertical transfer electrode 9 is set at intermediate level VM (FIG. 14D), so signal charges are stored only at the lower portions of the vertical transfer electrodes 7, 8, and 9 corresponding to the driving pulses xcfx86V2, xcfx86V3, and xcfx86V4, respectively, as shown in FIG. 15D.
At time t3, the driving pulse xcfx86V2 applied to the vertical transfer electrode 7 is set at low level VL (FIG. 14B), so signal charges are stored only at the lower portions of the vertical transfer electrodes 8 and 9 corresponding to the driving pulses xcfx86V3 and xcfx86V4, respectively, as shown in FIG. 15E.
At time t4, the driving pulse xcfx86V1 applied to the vertical transfer electrode 6 is set at intermediate level VM (FIG. 14A), so signal charges are stored only at the lower portions of the vertical transfer electrodes 8, 9, and 6 corresponding to the driving pulses xcfx86V3, xcfx86V4, and xcfx86V1, respectively, as shown in FIG. 15F.
At time t5, the driving pulse xcfx86V3 applied to the vertical transfer electrode 8 is set at low level VL (FIG. 14C), so signal charges are stored only at the lower portions of the vertical transfer electrodes 9 and 6 corresponding to the driving pulses xcfx86V4 and xcfx86V1, respectively, as shown in FIG. 15G.
By sequentially applying the driving pulses, the signal charges 30 are transferred to the left of the drawings, as shown in FIGS. 15A to 15G. Such a driving pulse application method is called double clocking. As the characteristic feature of this method, two or more electrodes are always set at intermediate level VM independently of the states during transfer.
The maximum amount of charges to be transferred by the vertical CCD 5 is limited by the state wherein the driving pulses applied to two vertical transfer electrodes adjacent in the vertical transfer direction are at intermediate level VM, and the driving pulses applied to the remaining vertical transfer electrodes are at low level VL, as at time t1, t3, or t5. That is, the maximum transfer charge amount of the vertical CCD 5 is determined by the amount of charges to be stored in two electrodes adjacent in the vertical transfer direction.
The signal charge read from the photodiode 4 to the vertical CCD 5 will be examined below. Signal charges stored in the photodiode 4 are read by applying a driving pulse of high level VH to the vertical transfer electrode 8 also serving as a transfer electrode. The read voltage required for a complete read depends on a read channel width W of the transfer gate region 10. More specifically, when the read channel width W is large, the read is complete with a low applied voltage.
On the other hand, when the read channel width W is small, the channel potential becomes low because of the narrow channel effect (i.e., the threshold voltage becomes high). Hence, unless a higher voltage is applied to the vertical transfer electrode 8 serving as a transfer electrode, a complete read cannot be performed.
As shown in FIG. 11, the four vertical transfer electrodes 6 to 9 are formed for each photodiode. In this case, when a vertical transfer electrode is equally divided such that all the vertical transfer electrodes 6 to 9 have equal electrode lengths in the transfer direction (L1=L2=L3=L4 in FIG. 13), the electrode length is about xc2xc the pixel size. For example, when the pixel size is 6.7 xcexcm2, and the electrode interval is 0.2 xcexcm, each of the electrode lengths L1, L2, L3, and L4 is 1.475 xcexcm. Hence, the read channel width W (=the electrode length L3 of the vertical transfer electrode 8) in the transfer gate region 10 is 1.475 xcexcm or less.
FIG. 16 shows a simulation result of the dependence of the read completion voltage on the read channel width W. As is apparent from FIG. 16, when the read channel width W in the transfer gate region 10 is 1.475 xcexcm, the read completion voltage is as high as about 15.5 V. When manufacturing variations are taken into consideration, the read pulse must be set at a voltage of 17.5 V or more, resulting in difficulty in lowering the voltage of a camera.
To avoid such an increase in read completion voltage, the following method can be employed. FIG. 17 shows the photodiodes 4 and vertical CCDs 5 of a CCD solid-state image sensing device having an increased read channel width W in the transfer gate region 10. FIG. 17 shows only 3xc3x972 pixels in the horizontal and vertical directions.
As the characteristic feature of the solid-state image sensing device shown in FIG. 17, the vertical transfer electrode 8 which is also used as a transfer electrode has a larger electrode length in the vertical transfer direction than the electrode lengths of the remaining vertical transfer electrodes. With this arrangement, the read channel width W in the transfer gate region 10 can be made larger, and a decrease in read voltage can be expected.
FIGS. 18A to 18G show potentials representing signal charge storage and transfer states in the solid-state image sensing device having the electrode structure shown in FIG. 17. The method of driving the vertical CCD 5 is the same as that of the solid-state image sensing device having the electrode structure shown in FIG. 11, and a detailed description thereof will be omitted.
In this solid-state image sensing device, the electrode lengths of the three vertical transfer electrodes 6, 7, and 9 other than the transfer electrode 8 in the vertical transfer direction are smaller than the electrode length of the transfer electrode 8. For this reason, at time t5, charges are stored at the lower portions of the two vertical transfer electrodes 6 and 9 having smaller electrode lengths. Since the maximum transfer charge amount of the vertical CCD 5 is limited by this charge storage state, the dynamic range becomes narrower than that of the solid-state image sensing device having the electrode structure shown in FIG. 11.
As described above, in the conventional solid-state image sensing device, the voltage can hardly be lowered. In addition, in the solid-state image sensing device whose read channel width in the transfer gate region is increased to realize a low voltage, the dynamic range becomes narrow.
It is an object of the present invention to provide a solid-state image sensing device capable of realizing a low voltage without decreasing the dynamic range (maximum transfer charge amount), and a method of driving the same.
In order to achieve the above object, according to the present invention, there is provided a solid-state image sensing device comprising photoelectric conversion elements two-dimensionally arrayed in a matrix on a semiconductor substrate, a transfer gate portion arranged adjacent to each of the photoelectric conversion elements to read signal charges stored in the photoelectric conversion element, a vertical CCD arranged adjacent to the transfer gate portion to transfer the signal charges read from the photoelectric conversion element in a vertical direction, a horizontal CCD for transferring the signal charges transferred from the vertical CCD in a horizontal direction, a charge detection portion for detecting the signal charges transferred from the horizontal CCD and outputting the signal charges, and four vertical transfer electrodes formed adjacent to each other on the vertical CCD in a vertical transfer direction of the signal charges, the vertical transfer electrodes including first and second transfer electrodes adjacent to each other in the vertical transfer direction of the signal charges, and the first vertical transfer electrode having a larger length than that of the second vertical transfer electrode and serving as a transfer electrode for controlling the transfer gate portion.